1. Field of the Invention
The present invention relates generally to testing semiconductor memory devices, and more specifically, to a semiconductor memory device having on-chip testing circuit for testing memory cells.
2. Description of the Background Art
As semiconductor memory devices have been highly integrated in recent years, drawbacks of which tend to be increased. Therefore, a test circuit of a semiconductor memory device is needed. In order to reduce test time, proposed or implemented is a provision of a test circuit in the semiconductor memory device.
FIG. 1 is a block diagram showing a conventional semiconductor memory device having a built-in test circuit which is described in the Japanese Patent Laying Open (KOKAI) No. 62-170100. In the drawing, the semiconductor memory device 1 comprises a memory cell array 2, a row address decoder 3, a column address decoder 4 and a sense amplifier 5, and is supplied with address signals A0-A7, a read/write signal W and write data D. Further, the semiconductor memory device 1 comprises a test circuit 6.
When the read/write signal W is a logical "0", write data D is written into cells selected by the address signals A0-A7. When the read/write signal W is a logical "1", contents of cells selected by the address signals A0-A7 are read out as RAM output 0.
The test circuit 6 built in the semiconductor memory device of FIG. 1 comprises a comparator C and a register R for storing test results.
The RAM output 0 is applied to one input of the comparator C, and an externally applied signal of expected value E is applied to the other input of the comparator C. When these two inputs are not coincident, the comparator C outputs a logical "0", which is applied to the register R. Before starting a test, the register R is set for the logical "1" by a set signal S. The register R accepts the contents of input when an externally inputted enable signal T is the logical "1". Once the register R becomes the logical "0", it holds the same unless a set signal S is applied. A test result signal F becomes the logical "0" only when the RAM output 0 and the signal of expected value E are not coincident in testing, so that the memory cell proves defective.
Now, testing operation of the semiconductor memory device shown in FIG. 1 will be described.
FIG. 2 is a diagram of a system structure showing one example of a memory testing system for testing the semiconductor memory device shown in FIG. 1.
In the memory testing system shown in FIG. 2, a memory testing machine TM provides to respective semiconductor memory devices M0-M3-Mn to be tested an input signal group D, a signal of expected value E, a set signal S for setting a register and an enable signal T indicating whether a register is to operate or not. Test results are detected by light emitting diodes L connected external to respective semiconductor memory devices. As a result of the test, if there is a defect, a light emitting diode L lights up, so that corresponding one of the semiconductor memory devices M0-Mn can be removed.
In this case, as far as driving capacity of the input signal driver of the memory testing machine TM permits, many semiconductor memory devices can be connected in parallel to be simultaneously tested.
As such memory testing machine TM as described above, for example, ANDO 8042, product of Ando Electric Co., Ltd. is known.
Since a conventional semiconductor memory device is structured as the above, a total of four terminals, that is, a terminal for inputting a signal of expected value E, a terminal for inputting a set signal S, a terminal for inputting an enable signal T and a terminal for outputting a test result F are necessary for a test circuit. Therefore, the number of pins becomes larger as compared with a standard semiconductor memory device without a built-in test circuit. As a result, it is not compatible with standard semiconductor memory devices, so that it is of little practice.
In addition, since a device for generating the foregoing signals E, S and T for a test is required, its test system becomes complicated, thereby making a memory test device expensive.